As is known in the art, it is frequently desirable to operate the amplifier linearly and with high efficiency over a wide range of input power levels. In order to design such a power amplifier, a fixed input impedance network is designed which compromises between performance at high input power levels and low input power levels.
As is also known in the art, Gallium Nitride (GaN) transistors are high band gap semiconductor devices that operate at high voltages (typically, 20 to 50V) and high current densities (up to 1.5 A/mm). The devices have been demonstrated to produce 6 W/mm for large periphery devices (over 2 mm) over the frequency range from 2 to 20 GHz. At still higher frequencies up to 40 GHz the transistors have been shown to produce up to 4 W/mm of output power.
One type of GaN includes a Gamma gate, (i.e., a gate with an overhang extending into the gate drain region sometimes also referred to as a field plate), as shown in FIG. 4. The purpose of the overhang is to reduce the fields in that region so that the transistor can be operated at high voltages to utilize the wide band gap properties of GaN. This is the type of transistor that is generally used in all our MMIC design applications at S-, C-, X- and Ku-bands. Transistors such as GaN are used to design high power amplifiers for use in military radars, communication and commercial base station applications. A power amplifier is usually designed to operate over a specified band of frequencies at a specified power level. At a given frequency within the band, the amplifier response is gauged by its transfer characteristics, i.e., output power versus the input power (drive). As the input drive is increased the output power is a linear function of the input power initially, but eventually reaches saturation or compression.
As is known, small signal means linear operation of a transistor (FET) and large signal means non-linear operation of the transistor. Linear operation, by definition, means minimal perturbation of a system or an amplifier. For an amplifier, with less than 20 dB of gain that produces 1 W of saturated output power, the application of an input drive power of a few milliwatts would be considered as linear operation. The response of the amplifier is given by a linear equation: Pout=(SS Gain)×Pin, where SS Gain is the small signal gain of the amplifier and is a constant in the equation. As Pin is increased this relationship holds up to an input drive level beyond which SS Gain is replaced by LS Gain (large signal gain), which is no longer, a constant. At a certain drive level LS Gain is lower than SS Gain by 1 dB and is the region in the Pout vs Pin transfer curve that is called 1 dB compression point. Beyond the 1 dB compression point a normal amplifier will follow the gain response of 1 dB drop in gain for 1 dB increase in Pin (1 dB/1 dB) as shown in FIG. 5. An amplifier that deviates from this gain response in the large signal region by displaying a slope of 1 dB/2 dB or 1 dB/3 dB and so on can be described as having soft compression.
At microwave frequencies where there is spatial and time dependence of voltage and current it is customary to use power instead of voltage. The voltage is proportional to square root of the power. Each power level of an amplifier corresponds to a voltage and current. In the small signal regime the voltage and current are sinusoidal. In the large signal regime sinusoidal inputs can lead to an output with distorted voltage and current shapes. So it becomes easier to talk in terms of power. In the small signal region the power can be obtained by simple multiplication of Voltage and Current. In the large signal region Power is integration of a complex voltage and current over a cycle.
Typical transfer characteristics of a transistor or a power amplifier are shown in FIG. 5, illustrating a linear region at the lower input power levels and a hard saturation region at the higher input power levels. Also plotted on the same FIG. 5 are solid lines illustrating transfer characteristics of an ideal transistor. Both curves have a common X-axis labeled Pin(dBm) (input drive level). The top curve is Pout or power out versus Pin. The bottom curve is Gain in dB vs Pin.
GaN based transistors with field plates and power amplifiers operating at high voltages have been observed to exhibit “soft compression” characteristics depicted by the dotted curve in the same FIG. 5. The 1 dB compression of the transistor occurs at Pin=9 dBm, while the “ideal” transistor saturates for Pin=13 dBm or greater. Because of soft compression the non-ideal FET will require a higher input drive level to obtain power saturation of the device and the amplifier designed with such FETs will also require a higher drive than normal. Furthermore, a 2-stage GaN amplifier will require a conservative choice of the FET ratio between stages, thereby contributing to reduced efficiency.
The method used to design an input impedance for the transistor has typically been as follows: First, the output tuner load is match to 50 Ohms. Next, a small signal source pull is used to determine best source match for the best output power. (A source or load pull refers to the technique of varying either the input or output match of the transistors around the Smith chart until the optimum performance is achieved.) Alternatively, the source match location on the Smith chart can also be obtained from S-parameters of the device at a predetermined frequency within the normal operating range of the device, here for example a frequency of 3 GHz. This source match is also called a small signal conjugate match to the input of the device. Next, with this fixed source match, a load pull is performed on the device from low to high drive levels. The drive level should be high enough to drive the output at least 3 dB into compression. Next, power and efficiency contours are generated from low to high drive levels and the location of the power and efficiency load targets are noted. Next, Pout versus Pin transfer curves are obtained at the power and efficiency load targets. The system also records Gt and Gp (transducer gain and power gain), reflected power from the device input (S11) or return loss among several other measurement related parameters. The transfer curves Pout vs Pin clearly exhibit soft compression characteristics, as shown in FIG. 5. Note the input drive level required to saturate the device.
Thus, when the input of the GaN devices is matched using the conventional small signal conjugate match or matched at low drive, the devices exhibit “soft” compression characteristics, rather than the 1 dB/1 dB hard compression knee that is desired, as displayed by the transfer characteristics of Pout vs Pin.
Applicants have discovered that there is significant degradation to amplifier efficiency at high input power levels using a fixed input impedance network, (i.e., an input impedance having components which are the same at both low input power levels and high input power levels). This significant degradation has been determined by the applicants when such input impedance networks are coupled to the gate electrode of transistors having field plates and with GaN transistor power amplifiers. More particularly, with regard to GaN transistors, such transistors have been found to exhibit soft compression (i.e., a gradual transition between a linear amplification region of the transistor and a non-linear amplification region of the transistor).
Still more particularly, applicants have discovered that soft compression in GaN devices can be significantly reduced or eliminated using a matching procedure at the input of the device with relatively large input signal drive levels rather than with relatively low signal input drive levels. More particularly, upon re-matching the device under large signal conditions or high drive and then sweeping the transfer curves at a power or efficiency power load, the soft compression features in the transfer characteristics are significantly removed or eliminated.
In accordance with the present invention, a circuit is provided having: an input matching network; a transistor coupled to an output of the impedance network; and wherein the input matching network has a first input impedance when such input matching network is fed with an input signal having a relatively low power level and wherein the input matching network has an input impedance different from the first input impedance when such input matching network is fed with an input signal having a relatively high power level.
In one embodiment, the transistor has a field plate.
In one embodiment, the transistor is a gallium nitride transistor.
In accordance with another feature of the invention, a circuit is provided having; a transistor having an input electrode; an input matching network having an input fed by an input signal and having an output connected to the input electrode of the transistors; a power level sensing circuit fed by the input signal; and wherein the input matching network is responsive to the power level sensing circuit to: configure the input matching network with a first input impedance when such power level sensing circuit senses the input signal has a relatively low power level; and configure the input matching network with an input impedance different from the first input impedance when such power level sensing circuit senses the input signal has a relatively high power level.
In one embodiment, the input matching network has a first inductor serially coupled between the input signal and the input electrode of the transistor when such power level sensing circuit senses the input signal has the relatively high level and wherein the input matching network has a second inductor serially coupled between the input signal and the input electrode of the transistor when such power level sensing circuit senses the input signal has the relatively low power level.
In one embodiment, the input matching network comprises a pair of electrical components and at least one switch. The switch operates in response to the power level sensing circuit to electrically decouple one of the pair of electrical components from the input matching network at one of the relatively high or relatively low power levels and operates to electrically couple said one of the pair of electrical components to the input matching network at the other one of the relatively high or relatively low power levels.
The invention thus incorporates an input signal power level dependent element (i.e., a configurable input matching network). First, an optimal small signal input matching network configuration is attached to the GaN transistor. This provides good stability, return loss, and power transfer from an RF input to the amplifying transistor at low drive powers (i.e., low signal power levels), but at the expense of poor performance under high drive powers (i.e., high signal power levels). The reconfigured input matching network is then used to rotate the phase angle (i.e., match), only under high input signal power levels, to that what is optimal for realizing peak performance without soft compression. For example, at S-band for a 2.5 mm periphery transistor, this input matching network will only have to rotate the original phase angle by 10 degree clockwise on the Smith Chart. The reconfigured input matching network is disconnected from the first via switches in the RF path, activated by a power sensing diode. Under higher drive powers, the power sensing diode and associated circuit would open the RF switches (depletion-mode switch operation), connecting the second matching network to the first, causing a rotation to the optimal large signal match point. The diode's size and bias would be chosen to “turn-on” at a set drive, based on amplifying stage FET periphery. With such an arrangement, the input matching network has a configuration to provide impedance matching at low input signal drive power levels and a different configuration so as to provided impedance matching at the high input signal drive power levels.
Thus, the invention incorporates a “smart”, tunable or configurable input matching network with a complex, just now understand, GaN soft compression issue. The invention provides an optimal solution to low and high drive stability and performance issues.
In accordance a method is provided for designing an input network for a GaN transistor device. The method includes: driving the device through the input network with a relatively large input signal power level; varying parameters of the input network with the output of the device at a predetermined output power level; measuring transfer function performance parameters of the device as the input network parameters are varied; and selecting the input network parameters from the measured transfer function performance parameters.
The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims.
Like reference symbols in the various drawings indicate like elements.